Power Side-channel Attack Resistant Circuit Designs of ARX Ciphers Using High-level Synthesis

In the Internet of Things (IoT) era, edge devices have been considerably diversified and are often designed using high-level synthesis (HLS) for improved design productivity. However, HLS tools were originally developed in a security-unaware manner, resulting vulnerabilities to power side-channel attacks (PSCAs), which serious threat IoT systems. Currently, impact applicability existing methods PSCA-resistant designs limited. this paper, we propose an effective HLS-based method ciphers implemented hardware. particular, focus on lightweight block composed addition/rotation/XOR (ARX)-based permutations study effects threshold implementation (which is one provably secure countermeasures against PSCAs) behavioral descriptions along with changes scheduling. The results obtained Welch’s t-test demonstrate that our proposed can successfully improve resistance PSCAs all ARX-based used as benchmarks.